1. Technical Field
The present invention relates to a memory access device such as a direct memory access controller (DMAC) or the like to be used as a peripheral device of a computer system.
2. Background Art
Nowadays, a computer system requires high-speed data transmission to and from a peripheral device, and is therefore often provided with a memory access device. In a parallel computer, too, data transfer among processors is an important issue. Consequently, a memory access device is also required in such a computer. When a general-purpose processor is used as such a memory access device, not only a complicate address calculation can be conducted, but also an address protection is achieved. Thus, a general-purpose processor is often used recently.
With reference to FIGS. 7 and 8, the following description will discuss the arrangement of a conventional memory access device in which a processor is used. FIG. 7 is a view illustrating the arrangement of a conventional memory access device and FIG. 8 is a timing chart of the memory access device in FIG. 7.
Shown in FIG. 7 are a memory 10 as an external device, a memory access device 20, a processor 30, a register 40 into which data are to be written from the memory access device 20, a printer 50 as a peripheral device, and a CRT device 51.
In the memory access device 20, a control register 32 is disposed for starting the memory access device 20 upon reception of an instruction from the processor 30.
Exception detecting means 4 is adapted to detect any of a variety of exceptions as to whether or not, at the time of a multi-user/multi-task operation, each address is nested in a predetermined range in order to protect the data in the memory of other users than the user himself or herself, whether or not an address for a breakpoint to be used for debug is identical with a predetermined value, and the like. Also shown in FIG. 7 are a read latch 26, a write address buffer 27, and a selector 8 for selecting either the write address buffer 27 or the read latch 26. An operating unit 12 and an internal register 13 are connected to each other by an internal bus 25. An instruction memory 18 is connected to a decoding memory 19. A bus controller 35 is adapted to control the data output timings of the read latch 26 and the write address buffer 27, and also to control the changeover of an output of the selector 8.
The memory 10, the memory access device 20, the register 40 and the peripheral device 50 are connected to one another by an address bus 11 and a data bus 33. The CRT device 51 is connected to the data bus 33 through an interface circuit 52.
The memory access device 20 having the arrangement above-mentioned will be operated in the following manner. Basically, the decoding unit 19 fetches and then decodes an instruction from the instruction memory 18, and then gives an instruction to the operating unit 12. The operating unit 12 makes a calculation through data communication to and from the internal register 13 via the internal bus 25. These operations are generally carried out in a four-stage pipeline of instruction fetch, register read, calculation and register write.
The following description will discuss how to access to the memory 10. For example, when the instruction decoded at the nth instruction fetch stage, has contents which indicate to read a data stored in the memory 10, the following operations are carried out. As shown in FIG. 8, the address is read from the internal register 13 at the register read stage and, with the use of the address thus read, the operating unit 12 calculates the address of the data to be read in the memory 10 at the calculation execution stage. Also, at the calculation execution stage, the address thus calculated is stored in the read latch 26 and the bus controller 35 controls the read latch 26 such that the address thus latched is supplied to the memory 10, and the data to be read in the memory 10 is then read. At the register write stage, the data thus read from the memory 10 is then stored in the internal register 13. The operations above-mentioned may correspond to a load instruction in terms of instruction codes. That is, "ld (r1) r2" refers to the operations of reading the contents of the address r1 of the memory 10 and storing the contents into the register r2 of the internal register 13.
On the other hand, when the instruction decoded at the mth instruction fetch stage has contents which indicate to store a data in the memory 10, the following operations are carried out. As shown in FIG. 8, the address is read from the internal register 13 at the register read stage, and the operating unit 12 calculates the address at which the data is to be written in the memory 10, at the calculation execution stage. At the register write stage, the address thus calculated is stored in the write address buffer 27. Then, the address thus stored and the data to be written, are supplied to the memory 10, and the data is actually written in the memory 10. As shown in the write operation in FIG. 8, such actual data writing is carried out after the register write stage and at the time when the bus controller 35 has detected vacancies of the address bus 11 and the data bus 33. The operations above-mentioned may correspond to a store instruction in terms of instruction codes. That is, "st (r1) r2" refers to the operations of storing the data r2 at the address r1 of the memory 10. The write address buffer 27 is a first-in first-out device for containing a plurality of sets each comprising an address and data to be written. While the memory 10 is not being used by other device, the bus controller 35 controls the write address buffer 27 such that the memory 10 is accessed based on each bottom address stored in the write address buffer 27. Until the write address buffer 27 is fully stored, a subsequent instruction can be executed.
A read or write operation for the memory 10 can be selected by the selector 8 which selects the read latch 26 or the write address buffer 27. However, a read operation has priority in general.
In both a read (ld) operation and a write (st) operation, exception detection by the exception detecting means 4 is carried out at the calculation execution stage, and an exception detecting operation is executed simultaneously with the generation of an address to be accessed. When an exception is detected, the exception detecting means 4 sends an exception signal to the processor 30. Through the interface circuit 52, the processor 30 causes the CRT device 51 to display the fact that the exception has been detected.
Such a conventional arrangement, however, presents the following problems. In each of reading a data from the memory and writing a data into the memory, a predetermined address is calculated and exception detection is subsequently carried out on the address thus calculated at the calculation stage as shown in FIG. 8. This lengthens the execution time of the calculation stage by a period of time required for such exception detection. Even though the period of time required for executing other stages of instruction fetch, register read and register write, is short, this period of time is determined, in a pipeline operation, as a period of time restrained by the execution time of the calculation stage. Thus, there is a likelihood that the calculation stage becomes a bottleneck (critical path). In particular, when desired to add an allowance for exception detection, the execution time of the calculation stage is further lengthened.
Further, in reading a data from the memory, there are carried out, at the calculation stage, read address calculation, exception detection and an operation of actually reading the data from the memory 10 with the use of the address thus calculated. Thus, the execution of the calculation stage takes much time. As the execution time of the calculation stage is lengthened, the effective performance is lowered.